1. Field Of the Invention
The present invention relates to direct memory access (DMA) controllers, and data path alignment logic used with such controllers. More particularly, the present invention relates to the application of data path aligners in peripheral devices such as network adaptors.
2. Description of Related Art
DMA controllers are used in computer systems for moving blocks of data from one location to the next, while relieving the host processor of the need to generate a long sequence of addresses to accomplish the move. The DMA controller is started by an event, and generates the addresses for moving data from a source location to a destination location. Typically the data is a large block of data which begins at a source address, and is moved to a destination beginning at a destination address. Such DMA controllers have wide spread application in the computer industry.
In many environments, a source memory may store data on double-word boundaries, each double-word consisting of four bytes of data. According to one conventional use of the terminology, a byte is composed of eight bits, a word is composed of 16 bits (two bytes), and a double-word is composed of 32 bits (four bytes).
The destination memory may also store double-words on each access to the memory. Thus, each read or write cycle involves accessing a double-word of memory from either the source or the destination memory.
In many computer systems, such as the EISA bus or Microchannel bus systems, while data may be stored on double-word boundaries, memories .storing the data may be addressed on byte or word boundaries. Thus, the beginning of a block of memory to be moved by a DMA access may reside on a byte, word or double-word boundary within the memory. Similarly, the destination to which this block of data is to move may begin on a byte, word or double-word boundary.
A problem arises when the starting address in the source does not align on byte boundaries with the starting address in the destination. For instance, if a starting word in the source memory includes the third and fourth bytes at a given double-word location, and the starting address in the destination memory begins with the second byte in a double-word location, the DMA system must provide for moving the data from the third and fourth positions to the second and third positions. After this transfer, the fourth position in the destination address remains empty. A second read to the source will retrieve four bytes of data from a next double-word location. However, the first byte must be stored in the fourth position of the first double-word location in the destination memory. This leaves three bytes for storage in the second double-word location in the destination memory. As can be seen, this data path alignment requires two read/write cycles per location in the destination memory to completely fill the destination memory.
It is desireable to provide a faster, more efficient mechanism for aligning the data from a source memory in a destination memory on byte, word and double-word boundaries. This is particularly critical in high speed applications, such as efficient network interface adaptor systems and the like.